1. Technical Field
The present invention relates to a circuit board and a semiconductor device.
2. Related Art
Conventionally, efforts for reducing source noise and ground noise have been implemented by incorporating a filter circuit or a decoupling capacitor into a source line, as a countermeasure for an electro magnet interference (EMI) caused in a printed circuit board that has devices such as LSI mounted thereon.
Typical conventional technologies related to such noise reduction includes a technology described in Japanese Patent Laid-Open No. 2006-237,314 and a technology described in Japanese Patent Laid-Open No. 2001-237,505.
Japanese Patent Laid-Open No. 2006-237,314 describes that a reduction in a generation of a radiated noise can be achieved by disposing a capacitor in a corner of a rectangular circuit board. In addition, it is also described that a reduction in a displacement of a standing wave can be more effectively achieved by disposing capacitors in a plurality of corners.
Japanese Patent Laid-Open No. 2006-237,314 also describes that capacitors are disposed in positions in a side of a circuit board equally distributed by diving the length of the side with n integer number “n” with equal intervals therebetween, in which a displacement of a standing wave generated due to a resonance is increased, so that a generation of a radiated noise is inhibited to reduce a fluctuation of voltage between a source interconnect layer and a ground interconnect layer with an improved efficiency. In addition, it is also described that additional capacitors are additionally disposed arbitrary sides of the circuit board in addition to providing capacitors in one side, so that a displacement of a standing wave is more effectively reduced. According to Japanese Patent Laid-Open No. 2006-237,314, it is described that smaller number of capacitors disposed in smaller number of positions equally distributed in the side of the circuit board with equal intervals therebetween allows further inhibition of a displacement of a standing wave, and in particular, if a capacitor is disposed in a position where a side of the circuit board is divided by two, a maximum reduction in a displacement of a standing wave can be achieved.
Further, Japanese Patent Laid-Open No. 2006-237,314 also describes that capacitors are provided so as to annularly surround an edge of the circuit board and have no section in the cyclic edge of the circuit board without being covered by a capacitor.
Japanese Patent Laid-Open No. 2001-237,505 describes a printed circuit board having a pattern of grounds provided in a periphery of a source interconnect in plane that also includes a source layer. It is also described that the electrodes are formed to have a zigzag-shape or an interdigit-shape in a section where the source interconnect faces the ground pattern. According to Japanese Patent Laid-Open No. 2001-237,505, it is described that a ground pattern is provided in a periphery of a source interconnect, so that capacitors are formed therebetween to provide an inhibition of a source noise reflected from an end of the printed circuit board. It is also described that the electrodes are formed to have a zigzag-shape or an interdigit-shape to provide an increased capacitance of a capacitor for terminal end, thereby further enhancing an advantageous effect of reducing a source noise.
On the contrary, though the technical field is not related to the present invention, Japanese Patent Laid-Open No. 2004-40,650 discloses a parallel plate track device, which is manufactured by disposing a dielectric film between two opposing metallic members so as to meander through the metallic, members to serve as a transmission line.
The present inventors investigated the technology described in Japanese Patent Laid-Open No. 2006-237,314, and found that there is a need to provide a reduced high frequency noise.
Relatively-low frequency noise can be improved to a certain extent by disposing capacitors on four corners or any sides of the rectangular circuit board as described in Japanese Patent Laid-Open No. 2006-237,314. On the contrary, when the frequency of noise is increased to, for example, 1 GHz or higher, it is difficult to effectively eliminate a source noise and a ground noise by simply arranging the capacitors in the ends of the rectangular circuit board, and if a noise is to be eliminated by the capacitors arranged along the side of the rectangular circuit board, a number of capacitors are required, and thus such approach is not effective.
Thus, residual high-frequency source noise and ground noise, which are not completely eliminated to remain, repeatedly reflect on the source interconnect in the circuit board and on a circumference of the source interconnect and the ground interconnect, creating resonance points in specified locations in a surface including the source interconnect and the ground interconnect, which are the reasons for creating larger common-mode noises.
A possible approach to eliminating a high-frequency noise may be a process for predicting positions of the resonance points created in the source interconnect and the ground interconnect, and then coupling decoupling capacitors in such positions. However, since the positions of the resonance points depend upon various factors such as positions of the devices serving as noise sources, frequency components of noise, type, number and position of decoupling capacitor, geometries of the source layer and the ground layer or the like, the prediction thereof by utilizing the conventional configuration is difficult.